About the role
Responsibilities:
- Design and verification of digital IP for CIS - Define chip level architecture taking into consideration power, performance & area trade-offs; build top level and module specification - Perform logic synthesis, work with backend team for floor planning, STA and DFT - Drive innovation and continuous improvement of design flow - Mentor junior team members - Participate in project planning and progress tracking - Full-chip integration and verification - Silicon bring-up, validation and debug
Qualifications:
- Minimum MSEE + at least 7 yrs. of digital design experience - Expertise in RTL design and verification for ASICs. - Experience handling logic synthesis and static timing analysis for multiple projects - Knowledge of all aspects of chip development cycle from design specification, architecture definition, low-power design, tape-out, to chip validation and debug - Technical lead experience is a plus - Knowledge of ASIL is a plus - Knowledge of DFT is a plus - Image processing/DSP knowledge is a plus - Excellent command of English as a working language is a must - Ability to work collaboratively with people across multiple functional areas
Please include a cover letter outlining your motivation to move to, live and work in Oslo, Norway.
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