About the role
Responsibilities:
As Digital Design Engineer, • Responsible for RTL design and verification using Verilog and System Verilog • Define System Architecture and/or Block level Micro Architecture based on product features and performance requirements, also with gate count and power estimation • Work closely with Analog Design Engineers to develop Sensor Timing Control logic • Implement Image Signal Processing blocks into System • Optimize Design for Low Power consumption • Work on Physical Design (Synthesis, Formal Verification, STA, DFT) • Silicon bring-up and production support
Requirements:
• 3+ year experience with RTL design and verification • Experience to develop Digital System on silicon • Strong debugging and problem-solving skills • Good communication and interpersonal skills • Result oriented and embrace change behaviors • Experience / knowledge in CMOS Image Sensor and/or Image Signal Processing is a plus • Experience / knowledge in mixed-signal design is a plus • Language skill: Japanese Business and English Business • Project management / People management experience and skill is a plus • MS / PhD in Electrical Electronics Engineering or related field, or equivalent work experience
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