About the role
Job Title: Sr. Analog Physical Design Engineer
Job Duties:
- Work on detailed column ADC circuit design, with a focus on column layout design. Collaborating with other column ADC designers to optimize column ADC’s performance with minimum silicon area. - Conduct cross products column ADC layout comparison and IP layout development and maintenance. - Perform RCX extraction of column circuit and critical signals parasitic analysis and propose optimized design to improve column ADC performance and image quality. - Conduct image sensor pixel array and column ADC supply analysis using Totem or other methodologies, including worst case P2P resistor extraction, and optimize chip floorplan and power routing. - Study design rules for new processes and provide physical design guidelines to the design team. Debug and develop Calibre svrf files when needed. - Apply SKILL script to improve productivity and design robustness. - Responsible for full-custom analog IC layout and physical verification (DRC/ANT/DFM/ERC/LVS) using industry-standard tools like Cadence Virtuoso and Calibre. - Execute top-level layout and coordinate layout resources and schedules for all modules. - Perform floor planning and placements including pad locations, power/clock domain planning, ESD, integration of AMS and digital blocks, and chip-level routing strategy. - Lead top-level implementation from floorplan through GDS tape-out. - Develop and maintain layout methodologies and documentation to ensure efficient and consistent design practices.
Requirements:
Require Master’s degree or foreign equivalent degree in Electrical Engineering, Electronics Engineering, or a closely related field.
Require 2 years of experience in CMOS image sensor IC layout design.
Require the following experience or skills:
- Semiconductor process and device fundamentals, with expertise in addressing advanced technology nodes challenges. - Experience in image sensor manufacturing technology, performance metrics, and system-level integration in camera applications. - Experience with industry standard EDA tools, such as Cadence Virtuoso, PVS, Spectre, Innovus, Skipper, Siemens Calibre, Synopsys Hspice, Design Compiler, IC Compiler, PrimeTime, Laker and P2P. - Front-end and back-end ASIC design flows. - Experience in stacked chip process flow and related design considerations. - Skills in interpreting physical verification reports (DRC, DFM, ERC, LVS, etc.) and understanding SVRF rule files. - Advanced layout skills such as common-centroid layouts, symmetrical layouts, use of dummy devices, matching, ESD, latch-up, antenna effects, etc. - Understanding of layout impact on device matching, noise coupling, guard-ring, electromigration, isolation and IR drop. - Developing CAD flow automation using scripting languages like Perl, Skill, and Tcl. - Expertise in low-power, high-precision, high speed analog layout design techniques. - Solving crosstalk challenges between adjacent column ADCs in image sensor circuits.
Annual base salary for this role in California, US is expected to be between $156,853 - $160,000. Actual pay will be determined on a number of factors such as relevant skills and experience, and the pay of employees in the similar role.
Text as published by OMNIVISION. We don't edit postings; apply and ask questions on the employer's site.