About the role
Lumotive is pioneering the era of programmable optics—where light is controlled as intelligently and flexibly as software.
At the heart of this transformation is a once-in-a-generation innovation: a flat CMOS-based “general purpose optic.” Lumotive’s Light Control Metasurface (LCM™) beam forming chips can be programmed to function as a beam steering mirror, a lens, mirror, a beam splitter—or any optical function—replacing bulky and mechanical optical components with a fully digital, reconfigurable semiconductor . This breakthrough lays the foundation for a massive shift in multiple technologies—from 3D sensing and imaging to optical networking, free space optical communication, and beyond. Like the shift from analog to digital in electronics, programmable optics will reshape industries from robotics, self-driving cars, AI, defense, and healthcare.
Lumotive’s first commercial application is in LiDAR, where its software-defined beam steering chips are already enabling compact, high-performance, solid-state sensors. These sensors are being deployed today in smart infrastructure, robotics, and mobility systems through leading module makers and solution integrators.
With more than 200 patents and growing commercial traction, Lumotive is delivering the world’s first digital platform for light—and redefining what’s possible in the optical age.
Job Description:
Lumotive is seeking a Principal Lead ASIC Design Implementation Engineer to lead the design and implementation of our mixed-signal beam-steering ASIC controller. As a hands-on lead, you will own the overall ASIC implementation flow and work closely with the physical design and analog design teams to bring the controller from RTL to tape-out. We’re looking for a seasoned, self-motivated leader with a thorough, detail-oriented approach who thrives in a multidisciplinary, fast-paced environment.
Responsibilities: • Lead full-chip ASIC implementation of a mixed-signal SOC controller, including integration of custom analog blocks at the digital top level. • Drive the P&R team to ensure smooth netlist handoffs and timely execution of P&R deliverables. • Participate in flow reviews with the P&R team to achieve the best PPA for all blocks. • Lead timing signoff for the post-P&R database.
Qualifications: • BS or MS in Electrical Engineering or a related field. • 12+ years of experience in ASIC implementation, preferably in networking, wireless, display controllers, touch controllers, or automotive sensor communication. • Strong experience with mixed-signal SoCs and the ASIC flow, with multiple successful tape-outs in advance process nodes. • Experience leading full-chip development of complex multi-processor SoC subsystems with bus fabrics and NoCs. • Hands-on experience with lint, CDC, synthesis, formal verification, DFT, and STA flows, including writing timing constraints at block and full-chip level. • Expertise in Verilog and SystemVerilog, and proficiency in Perl, Python, or similar scripting languages. • Experience integrating custom analog blocks into a digital top level. • Excellent analytical, debugging, and problem-solving skills. • Strong communication and teamwork abilities.
Benefits include but not limited to:
Health, dental and vision
FSA, HSA
PTO plus 14 paid company holidays
401K with 3% contribution
Stock Options
Life insurance and disability
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